When the processor is executing in Thumb state, which of the following statements is correct about the values stored in R15?

A. Bits[31:16] are duplicated with bits[15:0]

B. The PC value is stored in bits[31:1] and bit[0] is treated as zero

C. The PC value is stored in bits[31:16] and bits[15:0] are undefined

D. The PC value is stored in bits[15:0] and bits[31:16] are undefined

The following C function is compiled with hard floating point linkage.

float function(int a, float b, int c, float d);

Which register is used to pass argument c?

A. R0

B. R1

C. R2

D. R3

Which one of these statements is TRUE about code running on final hardware without a debugger attached?

A. It must start executing from RAM

B. RAM must be initialized before reset

C. Exception handlers must execute from ROM or flash memory

D. It must not execute semihosting SVC or BKPT instructions

Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?

A. An external DMA engine modifies data in a region of data memory which is already cached by the processor

B. An external agent needs to read data which has been modified by the processor in a cacheable memory region

C. Debugger reads data from a shared, cacheable memory location

D. One core modifies data in a shared cacheable memory region

Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)

A. Thumb is a hybrid 16/32-bit instruction set

B. No Thumb instructions can be conditionally executed

C. Thumb code is always slower than the equivalent ARM code

D. Some routines take more instructions in Thumb code than in the equivalent ARM code

E. The Thumb instruction set can access the Advanced SIMD "NEON" instructions

F. Thumb code is always more power-efficient than equivalent ARM code